IA32 Architecture Registers.

For simplicity we're using the same names for registers in 32 and 64 mode. For example, the A register, has a name rax on both 32-bit and 64-bit processors. However, on the former it is 32-bit (contrary to the name), and on the latter it is 64-bit.

include Bap.Std.CPU

A set of general purpose registers

val mem : Bap.Std.var


val sp : Bap.Std.var

Stack pointer

Flag registers
val zf : Bap.Std.var

zero flag

val cf : Bap.Std.var

carry flag

val vf : Bap.Std.var

overflow flag

val nf : Bap.Std.var

negative flag


val is_reg : Bap.Std.var -> bool

is_reg var true if var is a processor register

val is_flag : Bap.Std.var -> bool

is_flag reg is true if reg is a flag register

val is_sp : Bap.Std.var -> bool

is_sp x = Var.same x sp

val is_bp : Bap.Std.var -> bool

is_bp x is true if x can be possibly used as a base pointer register.

val is_zf : Bap.Std.var -> bool

is_zf x = Var.same x zf

val is_cf : Bap.Std.var -> bool

is_cf x = Var.same x cf

val is_vf : Bap.Std.var -> bool

is_vf x = Var.same x vf

val is_nf : Bap.Std.var -> bool

is_nf x = Var.same x nf

val is_mem : Bap.Std.var -> bool

is_mem x = Var.same x mem

val flags : Bap.Std.Var.Set.t

flags is a set of flag registers

val rbp : Bap.Std.var

base pointer

val rsp : Bap.Std.var

stack pointer

val rsi : Bap.Std.var

source index

val rdi : Bap.Std.var

destination index

val rip : Bap.Std.var

instruction pointer

val rax : Bap.Std.var

accumulator register

val rbx : Bap.Std.var

base register

val rcx : Bap.Std.var

counter register

val rdx : Bap.Std.var

data register

val ymms : Bap.Std.var array

YMM registers that are available