hardcaml

RTL Hardware Design in OCaml
Description

Hardcaml is an embedded DSL for designing and simulating hardware in OCaml. Generic hardware designs are easily expressed using features such as higher order functions, lists, maps etc. A built in simulator allows designs to be simulated within Hardcaml. Designs are converted to either Verilog or VHDL to interact with standard back end tooling.

Install
Documentation github.com Changelog MIT License Edit opam file
Published
25 Mar 2021
Authors
Maintainers
Sources
v0.14.2.tar.gz
md5=392c84bfcf1e9931f40bbbbb995f7b0a
Dependencies
zarith >= "1.5"
ppxlib >= "0.18.0"
dune >= "2.0.0"
topological_sort >= "v0.14" & < "v0.15"
stdio >= "v0.14" & < "v0.15"
ppx_sexp_conv >= "v0.14" & < "v0.15"
ppx_jane >= "v0.14" & < "v0.15"
base >= "v0.14" & < "v0.15"
ocaml >= "4.07.0"
Reverse Dependencies
hardcaml_waveterm = "v0.14.0"
ppx_deriving_hardcaml = "v0.14.0"