hardcaml
RTL Hardware Design in OCaml
Description
Hardcaml is an embedded DSL for designing and simulating hardware in OCaml. Generic hardware designs are easily expressed using features such as higher order functions, lists, maps etc. A built in simulator allows designs to be simulated within Hardcaml. Designs are converted to either Verilog or VHDL to interact with standard back end tooling.
Install
copied = false, 2000)"
:class="{ 'border-gray-700': !copied, 'text-gray-100': !copied, 'focus:ring-orange-500': !copied, 'focus:border-orange-500': !copied, 'border-green-600': copied, 'text-green-600': copied, 'focus:ring-green-500': copied, 'focus:border-green-500': copied }">
- Published
- 25 Mar 2021
- Authors
- Maintainers
Sources
Dependencies
zarith
>= "1.5"
ppxlib
>= "0.18.0"
dune
>= "2.0.0"
topological_sort
>= "v0.14" & < "v0.15"
stdio
>= "v0.14" & < "v0.15"
ppx_sexp_conv
>= "v0.14" & < "v0.15"
ppx_jane
>= "v0.14" & < "v0.15"
base
>= "v0.14" & < "v0.15"
ocaml
>= "4.07.0"
Reverse Dependencies
hardcaml_waveterm
= "v0.14.0"
ppx_deriving_hardcaml
= "v0.14.0"