hardcaml

RTL Hardware Design in OCaml
Description

Hardcaml is an embedded DSL for designing and simulating hardware in OCaml. Generic hardware designs are easily expressed using features such as higher order functions, lists, maps etc. A built in simulator allows designs to be simulated within Hardcaml. Designs are converted to either Verilog or VHDL to interact with standard back end tooling.

Install
Published
21 Mar 2022
Authors
Maintainers
Sources
hardcaml-v0.15.0.tar.gz
sha256=0dc4153de7ffa0a3471d9ecd8044f701e300290ce4c2e716187e063e8cf2f8b1
Dependencies
zarith >= "1.11"
ppxlib >= "0.23.0"
dune >= "2.0.0"
topological_sort >= "v0.15" & < "v0.16"
stdio >= "v0.15" & < "v0.16"
ppx_sexp_conv >= "v0.15" & < "v0.16"
ppx_jane >= "v0.15" & < "v0.16"
bin_prot >= "v0.15" & < "v0.16"
base >= "v0.15" & < "v0.16"
ocaml >= "4.11.0"
Reverse Dependencies