package hardcaml
RTL Hardware Design in OCaml
Install
Authors
Maintainers
Sources
hardcaml-v0.15.0.tar.gz
sha256=0dc4153de7ffa0a3471d9ecd8044f701e300290ce4c2e716187e063e8cf2f8b1
Description
Hardcaml is an embedded DSL for designing and simulating hardware in OCaml. Generic hardware designs are easily expressed using features such as higher order functions, lists, maps etc. A built in simulator allows designs to be simulated within Hardcaml. Designs are converted to either Verilog or VHDL to interact with standard back end tooling.
Published: 21 Mar 2022
Dependencies (10)
-
zarith
>= "1.11"
-
ppxlib
>= "0.23.0"
-
dune
>= "2.0.0"
-
topological_sort
>= "v0.15" & < "v0.16"
-
stdio
>= "v0.15" & < "v0.16"
-
ppx_sexp_conv
>= "v0.15" & < "v0.16"
-
ppx_jane
>= "v0.15" & < "v0.16"
-
bin_prot
>= "v0.15" & < "v0.16"
-
base
>= "v0.15" & < "v0.16"
-
ocaml
>= "4.11.0"
Dev Dependencies
Used by (11)
-
hardcaml_c
< "v0.16.0"
-
hardcaml_circuits
< "v0.16.0"
-
hardcaml_fixed_point
< "v0.16.0"
-
hardcaml_of_verilog
< "v0.16.0"
-
hardcaml_step_testbench
< "v0.16.0"
-
hardcaml_verify
< "v0.16.0"
-
hardcaml_verilator
< "v0.16.0"
-
hardcaml_waveterm
= "v0.15.0"
-
hardcaml_xilinx
< "v0.16.0"
-
hardcaml_xilinx_components
< "v0.16.0"
-
ppx_deriving_hardcaml
= "v0.15.0"
Conflicts
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