package hardcaml

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package hardcaml
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module Always : sig ... end

Always is a DSL that lets one describe a circuit in the same style as a Verliog always block.

module Architecture : sig ... end

Hardware architecture specification.

module Assertion_manager : sig ... end
module Bits : sig ... end

An immutable finite sequence of bits with a specified width.

module Build_mode : sig ... end

Specify whether to configure the hardware for simulation or synthesis.

module Caller_id : sig ... end

Embed the callstack in the signal type when it is created.

module Circuit : sig ... end

Creation and manipulation of hardware circuits

module Circuit_database : sig ... end

A database which holds a collection of circuits, indexed by a unique circuit name.

module Circuit_utilization : sig ... end

Utilization information for a circuit which can be printed to a sexp.

module Comb : sig ... end

Combinational logic API.

module Combinational_op : sig ... end

A custom combinational operation that can be inserted into a simulation.

module Combinational_ops_database : sig ... end

A database which holds a collecton of custom combinational operations for use with Cyclesim based simulators.

module Constant : sig ... end

Representation of variable width Constants and conversion to/from OCaml types.

module Cyclesim : sig ... end

Cycle accurate simulator

module Cyclesim_float_ops : sig ... end

Floating point operations for simulation.

module Design_rule_checks : sig ... end

Simple circuit analsysis passes for common issues.

module Dedup : sig ... end

Deduplicates combinatorial nodes performing redundant computation.

module Edge : sig ... end

Specification of rising or falling edge of a signal (normally a clock).

module Fifo : sig ... end

Synchronous FIFO implementions with optional showahead functionality and pipelining stages.

module Graph : sig ... end

Write circuit as graph.

module Hierarchy : sig ... end

Allow a hardcaml circuit to be defined as a hierarchy of modules, rather than just a single flat module.

module IntbitsList : sig ... end

Bits described as lists of ints ie 0;1;1;1;0 - width implicit as length of list

module Interface : sig ... end

Interfaces specify the widths and names of a group of signals, and some functions for manipulating the signals as a group.

module Instantiation : sig ... end

Instantiation of sub-modules.

module Level : sig ... end

Specification of a signals level - high or low.

module Mangler : sig ... end

Map a set of names to a set of unique names.

module Parameter : sig ... end

A Parameter.t is the name and value of a configurable attribute of an instantiated RTL design.

module Parameter_name : sig ... end

RTL name of parameters on instantiated modules.

module Property : sig ... end
module Property_manager : sig ... end
module Ram : sig ... end

Random access memories described using RTL inference.

module Recipe : sig ... end

Hardware generation in an imperative style.

module Reg_spec : sig ... end

Definition of clock, reset and clear signals for sequential logic (ie registers).

module Reserved_words : sig ... end

Tables of reserved words in Verilog, VHDL and OCaml.

module Rtl : sig ... end

VHDL and Verilog netlist generation

module Rtl_attribute : sig ... end

RTL attribute specification. Only relevant to downstream tooling.

module Scope : sig ... end

Scopes control the process of hierarchical circuit generation.

module Side : sig ... end

Used to specify when an operation should be performed - before or after an event like a clock edge.

module Signal : sig ... end

Hardware design datatype suitable for simulation and netlist generation

module Signal_graph : sig ... end

A Signal_graph.t is a created from a list of signals, and defined by tracing back to inputs (unassigned wires or constants). Functions are provided for traversing the graph.

module Structural : sig ... end

Hardware generation API that includes tri-states - used for toplevel module generation.

module Transform : sig ... end

Transform circuits to a different representation.

module Vcd : sig ... end

VCD (Verilog Change Dump) generation

module With_valid : sig ... end

Uses a valid bit to indicate the validity of a value. Conceptually similar to an Option.t.

val sexp_of_array : ('a -> Sexplib0.Sexp.t) -> 'a Base.array -> Sexplib0.Sexp.t

These are exposed for code that does @@deriving sexp_of, hardcaml.

val sexp_of_list : ('a -> Sexplib0.Sexp.t) -> 'a Base.list -> Sexplib0.Sexp.t