hardcaml

RTL Hardware Design in OCaml
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Library hardcaml
Module Hardcaml . Always . Variable
type internal
type t = private {
value : Signal.t;
internal : internal;
}
val internal : t -> internal
val value : t -> Signal.t
module Fields : sig ... end
val sexp_of_t : t -> Sexplib0.Sexp.t
val wire : default:Signal.t -> t

create a wire

val reg : ?enable:Signal.t -> width:Base.int -> Reg_spec.t -> t

create a register

val pipeline : ?enable:Signal.t -> width:Base.int -> depth:Base.int -> Reg_spec.t -> t

create a pipeline of registers