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package hardcaml_verilator
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module I : Hardcaml.Interface.Smodule O : Hardcaml.Interface.SSignature
val create :
(clock_names:string list ->
(Hardcaml.Signal.t I.t -> Hardcaml.Signal.t O.t) ->
(Hardcaml.Bits.t Stdlib.ref I.t, Hardcaml.Bits.t Stdlib.ref O.t)
Hardcaml.Cyclesim.t)
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