package hardcaml

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  2. Docs
RTL Hardware Design in OCaml


Dune Dependency






Hardcaml is an OCaml library for designing and testing hardware designs.

  • Express hardware designs in OCaml

  • Make generic designs using higher order functions, lists, maps, functors...

  • Simulate designs in OCaml

  • Convert to (hierarchical) Verilog or VHDL

  • Write new modules to transform or analyse circuits, or provide new backends


$ opam install hardcaml ppx_deriving_hardcaml hardcaml_waveterm


Tools and libraries

  • Hardcaml_waveterm - ASCII based digital waveforms. Usable in expect tests or from an interactive terminal application.

  • Hardcaml_c - convert Hardcaml designs to C-based simulation models. Provides an API compatible with the standard Cyclesim module. Trades compilation time for runtime performance.

  • Hardcaml_verilator - Convert Hardcaml designs to very high speed simulation model using the open source Verilator compiler.

  • Hardcaml_step_testbench - Monadic testbench API. Control multiple tasks synchronized to a clock without converting to a statemachine coding style.

  • Hardcaml_circuits - A library of useful/interesting Hardcaml designs

  • Hardcaml_fixed_point - Fixed point arithmetic with rounding and overflow control

  • Hardcaml_xilinx - Various Xilinx primitives wrapped with Hardcaml interfaces and simulation models

  • Hardcaml_xilinx_components - Tool to read Xilinx unisim and xpm component definitions and generate Hardcaml interfaces

  • Hardcaml_of_verilog - Convert a verilog design to Hardcaml using Yosys

  • Hardcaml_verify - SAT based formal verification tools for Hardcaml

  • Hardcaml_xilinx_reports - Automated generation of synthesis reports from Vivado.

Projects using Hardcaml