package hardcaml_of_verilog

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type t
include Sexplib0.Sexpable.S with type t := t
val t_of_sexp : Sexplib0__.Sexp.t -> t
val sexp_of_t : t -> Sexplib0__.Sexp.t
include Ppx_compare_lib.Equal.S with type t := t
val equal : t Base__Ppx_compare_lib.equal
val create : name:Base.string -> value:Define_value.t -> t
val name : t -> Base.string
val value : t -> Define_value.t
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