hardcaml_xilinx_reports v0.16.0

val bitslice : t Variantslib.Variant.t

val dci_reset : t Variantslib.Variant.t

val input_buffer : t Variantslib.Variant.t

val delay : t Variantslib.Variant.t

val bidir_buffer : t Variantslib.Variant.t

val serdes : t Variantslib.Variant.t

val weak_driver : t Variantslib.Variant.t

val output_buffer : t Variantslib.Variant.t

val sdr : t Variantslib.Variant.t

val metastability : t Variantslib.Variant.t

val ddr : t Variantslib.Variant.t

val latch : t Variantslib.Variant.t

val fold : 
  init:'acc__0 ->
  bitslice:('acc__0 -> t Variantslib.Variant.t -> 'acc__1) ->
  dci_reset:('acc__1 -> t Variantslib.Variant.t -> 'acc__2) ->
  input_buffer:('acc__2 -> t Variantslib.Variant.t -> 'acc__3) ->
  delay:('acc__3 -> t Variantslib.Variant.t -> 'acc__4) ->
  bidir_buffer:('acc__4 -> t Variantslib.Variant.t -> 'acc__5) ->
  serdes:('acc__5 -> t Variantslib.Variant.t -> 'acc__6) ->
  weak_driver:('acc__6 -> t Variantslib.Variant.t -> 'acc__7) ->
  output_buffer:('acc__7 -> t Variantslib.Variant.t -> 'acc__8) ->
  sdr:('acc__8 -> t Variantslib.Variant.t -> 'acc__9) ->
  metastability:('acc__9 -> t Variantslib.Variant.t -> 'acc__10) ->
  ddr:('acc__10 -> t Variantslib.Variant.t -> 'acc__11) ->
  latch:('acc__11 -> t Variantslib.Variant.t -> 'acc__12) ->
  'acc__12

val iter : 
  bitslice:(t Variantslib.Variant.t -> Base.Unit.t) ->
  dci_reset:(t Variantslib.Variant.t -> Base.Unit.t) ->
  input_buffer:(t Variantslib.Variant.t -> Base.Unit.t) ->
  delay:(t Variantslib.Variant.t -> Base.Unit.t) ->
  bidir_buffer:(t Variantslib.Variant.t -> Base.Unit.t) ->
  serdes:(t Variantslib.Variant.t -> Base.Unit.t) ->
  weak_driver:(t Variantslib.Variant.t -> Base.Unit.t) ->
  output_buffer:(t Variantslib.Variant.t -> Base.Unit.t) ->
  sdr:(t Variantslib.Variant.t -> Base.Unit.t) ->
  metastability:(t Variantslib.Variant.t -> Base.Unit.t) ->
  ddr:(t Variantslib.Variant.t -> Base.Unit.t) ->
  latch:(t Variantslib.Variant.t -> Base.Unit.t) ->
  Base.Unit.t

val map : 
  t ->
  bitslice:(t Variantslib.Variant.t -> 'result__) ->
  dci_reset:(t Variantslib.Variant.t -> 'result__) ->
  input_buffer:(t Variantslib.Variant.t -> 'result__) ->
  delay:(t Variantslib.Variant.t -> 'result__) ->
  bidir_buffer:(t Variantslib.Variant.t -> 'result__) ->
  serdes:(t Variantslib.Variant.t -> 'result__) ->
  weak_driver:(t Variantslib.Variant.t -> 'result__) ->
  output_buffer:(t Variantslib.Variant.t -> 'result__) ->
  sdr:(t Variantslib.Variant.t -> 'result__) ->
  metastability:(t Variantslib.Variant.t -> 'result__) ->
  ddr:(t Variantslib.Variant.t -> 'result__) ->
  latch:(t Variantslib.Variant.t -> 'result__) ->
  'result__

val make_matcher : 
  bitslice:
    (t Variantslib.Variant.t ->
      'acc__0 ->
      (Base.Unit.t -> 'result__) * 'acc__1) ->
  dci_reset:
    (t Variantslib.Variant.t ->
      'acc__1 ->
      (Base.Unit.t -> 'result__) * 'acc__2) ->
  input_buffer:
    (t Variantslib.Variant.t ->
      'acc__2 ->
      (Base.Unit.t -> 'result__) * 'acc__3) ->
  delay:
    (t Variantslib.Variant.t ->
      'acc__3 ->
      (Base.Unit.t -> 'result__) * 'acc__4) ->
  bidir_buffer:
    (t Variantslib.Variant.t ->
      'acc__4 ->
      (Base.Unit.t -> 'result__) * 'acc__5) ->
  serdes:
    (t Variantslib.Variant.t ->
      'acc__5 ->
      (Base.Unit.t -> 'result__) * 'acc__6) ->
  weak_driver:
    (t Variantslib.Variant.t ->
      'acc__6 ->
      (Base.Unit.t -> 'result__) * 'acc__7) ->
  output_buffer:
    (t Variantslib.Variant.t ->
      'acc__7 ->
      (Base.Unit.t -> 'result__) * 'acc__8) ->
  sdr:
    (t Variantslib.Variant.t ->
      'acc__8 ->
      (Base.Unit.t -> 'result__) * 'acc__9) ->
  metastability:
    (t Variantslib.Variant.t ->
      'acc__9 ->
      (Base.Unit.t -> 'result__) * 'acc__10) ->
  ddr:
    (t Variantslib.Variant.t ->
      'acc__10 ->
      (Base.Unit.t -> 'result__) * 'acc__11) ->
  latch:
    (t Variantslib.Variant.t ->
      'acc__11 ->
      (Base.Unit.t -> 'result__) * 'acc__12) ->
  'acc__0 ->
  (t -> 'result__) * 'acc__12

val to_rank : t -> Base.Int.t

val to_name : t -> Base.String.t

val descriptions : (Base.String.t * Base.Int.t) Base.List.t

package hardcaml_xilinx_reports