hardcaml_xilinx_reports v0.16.0

val advanced : (Advanced.t Base.List.t -> t) Variantslib.Variant.t

val arithmetic : (Arithmetic.t Base.List.t -> t) Variantslib.Variant.t

val blockram : (Blockram.t Base.List.t -> t) Variantslib.Variant.t

val clb : (Clb.t Base.List.t -> t) Variantslib.Variant.t

val clock : (Clock.t Base.List.t -> t) Variantslib.Variant.t

val configuration : (Configuration.t Base.List.t -> t) Variantslib.Variant.t

val io : (Io.t Base.List.t -> t) Variantslib.Variant.t

val register : (Register.t Base.List.t -> t) Variantslib.Variant.t

val fold : 
  init:'acc__0 ->
  advanced:
    ('acc__0 -> (Advanced.t Base.List.t -> t) Variantslib.Variant.t -> 'acc__1) ->
  arithmetic:
    ('acc__1 ->
      (Arithmetic.t Base.List.t -> t) Variantslib.Variant.t ->
      'acc__2) ->
  blockram:
    ('acc__2 -> (Blockram.t Base.List.t -> t) Variantslib.Variant.t -> 'acc__3) ->
  clb:('acc__3 -> (Clb.t Base.List.t -> t) Variantslib.Variant.t -> 'acc__4) ->
  clock:
    ('acc__4 -> (Clock.t Base.List.t -> t) Variantslib.Variant.t -> 'acc__5) ->
  configuration:
    ('acc__5 ->
      (Configuration.t Base.List.t -> t) Variantslib.Variant.t ->
      'acc__6) ->
  io:('acc__6 -> (Io.t Base.List.t -> t) Variantslib.Variant.t -> 'acc__7) ->
  register:
    ('acc__7 -> (Register.t Base.List.t -> t) Variantslib.Variant.t -> 'acc__8) ->
  'acc__8

val iter : 
  advanced:((Advanced.t Base.List.t -> t) Variantslib.Variant.t -> Base.Unit.t) ->
  arithmetic:
    ((Arithmetic.t Base.List.t -> t) Variantslib.Variant.t -> Base.Unit.t) ->
  blockram:((Blockram.t Base.List.t -> t) Variantslib.Variant.t -> Base.Unit.t) ->
  clb:((Clb.t Base.List.t -> t) Variantslib.Variant.t -> Base.Unit.t) ->
  clock:((Clock.t Base.List.t -> t) Variantslib.Variant.t -> Base.Unit.t) ->
  configuration:
    ((Configuration.t Base.List.t -> t) Variantslib.Variant.t -> Base.Unit.t) ->
  io:((Io.t Base.List.t -> t) Variantslib.Variant.t -> Base.Unit.t) ->
  register:((Register.t Base.List.t -> t) Variantslib.Variant.t -> Base.Unit.t) ->
  Base.Unit.t

val map : 
  t ->
  advanced:
    ((Advanced.t Base.List.t -> t) Variantslib.Variant.t ->
      Advanced.t Base.List.t ->
      'result__) ->
  arithmetic:
    ((Arithmetic.t Base.List.t -> t) Variantslib.Variant.t ->
      Arithmetic.t Base.List.t ->
      'result__) ->
  blockram:
    ((Blockram.t Base.List.t -> t) Variantslib.Variant.t ->
      Blockram.t Base.List.t ->
      'result__) ->
  clb:
    ((Clb.t Base.List.t -> t) Variantslib.Variant.t ->
      Clb.t Base.List.t ->
      'result__) ->
  clock:
    ((Clock.t Base.List.t -> t) Variantslib.Variant.t ->
      Clock.t Base.List.t ->
      'result__) ->
  configuration:
    ((Configuration.t Base.List.t -> t) Variantslib.Variant.t ->
      Configuration.t Base.List.t ->
      'result__) ->
  io:
    ((Io.t Base.List.t -> t) Variantslib.Variant.t ->
      Io.t Base.List.t ->
      'result__) ->
  register:
    ((Register.t Base.List.t -> t) Variantslib.Variant.t ->
      Register.t Base.List.t ->
      'result__) ->
  'result__

val make_matcher : 
  advanced:
    ((Advanced.t Base.List.t -> t) Variantslib.Variant.t ->
      'acc__0 ->
      (Advanced.t Base.List.t -> 'result__) * 'acc__1) ->
  arithmetic:
    ((Arithmetic.t Base.List.t -> t) Variantslib.Variant.t ->
      'acc__1 ->
      (Arithmetic.t Base.List.t -> 'result__) * 'acc__2) ->
  blockram:
    ((Blockram.t Base.List.t -> t) Variantslib.Variant.t ->
      'acc__2 ->
      (Blockram.t Base.List.t -> 'result__) * 'acc__3) ->
  clb:
    ((Clb.t Base.List.t -> t) Variantslib.Variant.t ->
      'acc__3 ->
      (Clb.t Base.List.t -> 'result__) * 'acc__4) ->
  clock:
    ((Clock.t Base.List.t -> t) Variantslib.Variant.t ->
      'acc__4 ->
      (Clock.t Base.List.t -> 'result__) * 'acc__5) ->
  configuration:
    ((Configuration.t Base.List.t -> t) Variantslib.Variant.t ->
      'acc__5 ->
      (Configuration.t Base.List.t -> 'result__) * 'acc__6) ->
  io:
    ((Io.t Base.List.t -> t) Variantslib.Variant.t ->
      'acc__6 ->
      (Io.t Base.List.t -> 'result__) * 'acc__7) ->
  register:
    ((Register.t Base.List.t -> t) Variantslib.Variant.t ->
      'acc__7 ->
      (Register.t Base.List.t -> 'result__) * 'acc__8) ->
  'acc__0 ->
  (t -> 'result__) * 'acc__8

val to_rank : t -> Base.Int.t

val to_name : t -> Base.String.t

val descriptions : (Base.String.t * Base.Int.t) Base.List.t

package hardcaml_xilinx_reports