package hardcaml

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package hardcaml
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type delta_message = {
  1. sets : (int * int32 list) list;
  2. gets : int list;
  3. delta_time : int64;
}

run sets, then gets then schedule next callback at cur_time+delta_time

type init_message = string list

expected inputs and outputs

type control_message =
  1. | Finish
  2. | Run of delta_message

control message

type response_message = (int * int32 list) list

response message

val net_addr : string
val net_port : int
module Comms : sig ... end

basic TCP communications between client (simulation) and server (hardcaml)

send a control message to the simulation

val write_testbench : ?dump_file:string -> name:string -> inputs:(string * int) list -> outputs:(string * int) list -> (string -> unit) -> unit

write test harness

val write_testbench_from_circuit : ?dump_file:string -> (string -> unit) -> Circuit.t -> unit

write test hardness derivied from a hardcaml circuit

val derive_clocks_and_resets : Circuit.t -> string list * string list

find clocks and resets in a hardcaml circuit

module type Simulator = sig ... end
module Icarus : Simulator
module Mti32 : Simulator
module Mti64 : Simulator
module Make (SIM : Simulator) : sig ... end