package hardcaml

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Class type
val bit : (Hardcaml__.Import.Bool.t -> t) Variantslib.Variant.t
val bit_vector : (Bit_vector.t -> t) Variantslib.Variant.t
val bool : (Hardcaml__.Import.Bool.t -> t) Variantslib.Variant.t
val int : (Base.Int.t -> t) Variantslib.Variant.t
val real : (Hardcaml__.Import.Float.t -> t) Variantslib.Variant.t
val std_logic : (Std_logic.t -> t) Variantslib.Variant.t
val std_logic_vector : (Std_logic_vector.t -> t) Variantslib.Variant.t
val std_ulogic : (Std_logic.t -> t) Variantslib.Variant.t
val std_ulogic_vector : (Std_logic_vector.t -> t) Variantslib.Variant.t
val string : (Hardcaml__.Import.String.t -> t) Variantslib.Variant.t
val fold : init:'acc__ -> bit: ('acc__ -> (Hardcaml__.Import.Bool.t -> t) Variantslib.Variant.t -> 'acc__) -> bit_vector:('acc__ -> (Bit_vector.t -> t) Variantslib.Variant.t -> 'acc__) -> bool: ('acc__ -> (Hardcaml__.Import.Bool.t -> t) Variantslib.Variant.t -> 'acc__) -> int:('acc__ -> (Base.Int.t -> t) Variantslib.Variant.t -> 'acc__) -> real: ('acc__ -> (Hardcaml__.Import.Float.t -> t) Variantslib.Variant.t -> 'acc__) -> std_logic:('acc__ -> (Std_logic.t -> t) Variantslib.Variant.t -> 'acc__) -> std_logic_vector: ('acc__ -> (Std_logic_vector.t -> t) Variantslib.Variant.t -> 'acc__) -> std_ulogic:('acc__ -> (Std_logic.t -> t) Variantslib.Variant.t -> 'acc__) -> std_ulogic_vector: ('acc__ -> (Std_logic_vector.t -> t) Variantslib.Variant.t -> 'acc__) -> string: ('acc__ -> (Hardcaml__.Import.String.t -> t) Variantslib.Variant.t -> 'acc__) -> 'acc__
val iter : bit: ((Hardcaml__.Import.Bool.t -> t) Variantslib.Variant.t -> Hardcaml__.Import.Unit.t) -> bit_vector: ((Bit_vector.t -> t) Variantslib.Variant.t -> Hardcaml__.Import.Unit.t) -> bool: ((Hardcaml__.Import.Bool.t -> t) Variantslib.Variant.t -> Hardcaml__.Import.Unit.t) -> int:((Base.Int.t -> t) Variantslib.Variant.t -> Hardcaml__.Import.Unit.t) -> real: ((Hardcaml__.Import.Float.t -> t) Variantslib.Variant.t -> Hardcaml__.Import.Unit.t) -> std_logic: ((Std_logic.t -> t) Variantslib.Variant.t -> Hardcaml__.Import.Unit.t) -> std_logic_vector: ((Std_logic_vector.t -> t) Variantslib.Variant.t -> Hardcaml__.Import.Unit.t) -> std_ulogic: ((Std_logic.t -> t) Variantslib.Variant.t -> Hardcaml__.Import.Unit.t) -> std_ulogic_vector: ((Std_logic_vector.t -> t) Variantslib.Variant.t -> Hardcaml__.Import.Unit.t) -> string: ((Hardcaml__.Import.String.t -> t) Variantslib.Variant.t -> Hardcaml__.Import.Unit.t) -> Hardcaml__.Import.Unit.t
val map : t -> bit: ((Hardcaml__.Import.Bool.t -> t) Variantslib.Variant.t -> Hardcaml__.Import.Bool.t -> 'result__) -> bit_vector: ((Bit_vector.t -> t) Variantslib.Variant.t -> Bit_vector.t -> 'result__) -> bool: ((Hardcaml__.Import.Bool.t -> t) Variantslib.Variant.t -> Hardcaml__.Import.Bool.t -> 'result__) -> int:((Base.Int.t -> t) Variantslib.Variant.t -> Base.Int.t -> 'result__) -> real: ((Hardcaml__.Import.Float.t -> t) Variantslib.Variant.t -> Hardcaml__.Import.Float.t -> 'result__) -> std_logic: ((Std_logic.t -> t) Variantslib.Variant.t -> Std_logic.t -> 'result__) -> std_logic_vector: ((Std_logic_vector.t -> t) Variantslib.Variant.t -> Std_logic_vector.t -> 'result__) -> std_ulogic: ((Std_logic.t -> t) Variantslib.Variant.t -> Std_logic.t -> 'result__) -> std_ulogic_vector: ((Std_logic_vector.t -> t) Variantslib.Variant.t -> Std_logic_vector.t -> 'result__) -> string: ((Hardcaml__.Import.String.t -> t) Variantslib.Variant.t -> Hardcaml__.Import.String.t -> 'result__) -> 'result__
val make_matcher : bit: ((Hardcaml__.Import.Bool.t -> t) Variantslib.Variant.t -> 'acc__0 -> (Hardcaml__.Import.Bool.t -> 'result__) * 'acc__1) -> bit_vector: ((Bit_vector.t -> t) Variantslib.Variant.t -> 'acc__1 -> (Bit_vector.t -> 'result__) * 'acc__2) -> bool: ((Hardcaml__.Import.Bool.t -> t) Variantslib.Variant.t -> 'acc__2 -> (Hardcaml__.Import.Bool.t -> 'result__) * 'acc__3) -> int: ((Base.Int.t -> t) Variantslib.Variant.t -> 'acc__3 -> (Base.Int.t -> 'result__) * 'acc__4) -> real: ((Hardcaml__.Import.Float.t -> t) Variantslib.Variant.t -> 'acc__4 -> (Hardcaml__.Import.Float.t -> 'result__) * 'acc__5) -> std_logic: ((Std_logic.t -> t) Variantslib.Variant.t -> 'acc__5 -> (Std_logic.t -> 'result__) * 'acc__6) -> std_logic_vector: ((Std_logic_vector.t -> t) Variantslib.Variant.t -> 'acc__6 -> (Std_logic_vector.t -> 'result__) * 'acc__7) -> std_ulogic: ((Std_logic.t -> t) Variantslib.Variant.t -> 'acc__7 -> (Std_logic.t -> 'result__) * 'acc__8) -> std_ulogic_vector: ((Std_logic_vector.t -> t) Variantslib.Variant.t -> 'acc__8 -> (Std_logic_vector.t -> 'result__) * 'acc__9) -> string: ((Hardcaml__.Import.String.t -> t) Variantslib.Variant.t -> 'acc__9 -> (Hardcaml__.Import.String.t -> 'result__) * 'acc__10) -> 'acc__0 -> (t -> 'result__) * 'acc__10
val to_rank : t -> Base.Int.t
val to_name : t -> Hardcaml__.Import.String.t
val descriptions : (Hardcaml__.Import.String.t * Base.Int.t) Hardcaml__.Import.List.t
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