package hardcaml_circuits

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package hardcaml_circuits
Legend:
Library
Module
Module type
Parameter
Class
Class type

Parameters

Signature

module I : sig ... end
module O : sig ... end
val create : cut_through:bool -> capacity:int -> Hardcaml.Scope.t -> Hardcaml.Signal.t I.t -> Hardcaml.Signal.t O.t

Creates a combinational fifo showahead fifo. Namely, rd_valid will be asserted whenever at the same cycle data is written into the fifo. The data will be held at the output of the fifo until read_enable is asserted.

The actual capacity of the fifo is capacity + 1, due to additional registering. Note that when o.full is asserted, i.wr_enable is ignored, even if rd_enable is asserted at the same cycle.

Raises an exception if capacity < 1.

val hierarchical : ?instance:string -> cut_through:bool -> capacity:int -> Hardcaml.Scope.t -> Hardcaml.Signal.t I.t -> Hardcaml.Signal.t O.t