package hardcaml_of_verilog

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type t = {
  1. module_name : Base.string;
  2. instance_name : Base.string;
  3. parameters : Parameter.t Base.list;
  4. inputs : Bus.t Port.t Base.list;
  5. outputs : Bus.t Port.t Base.list;
}
val sexp_of_t : t -> Sexplib0.Sexp.t
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