package hardcaml_xilinx

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General purpose 1D read ports.

type 'a t = {
  1. address : 'a;
  2. enable : 'a;
}
val sexp_of_t : ('a -> Sexplib0.Sexp.t) -> 'a t -> Sexplib0.Sexp.t
module type S = Hardcaml.Interface.S with type 'a t = 'a t
module Specialize (_ : Widths_1d) : S

Specialize a Read_port_1d.t given widths.

Specialize a Read_port_1d.t given a memory configuration.