package hardcaml_xilinx_reports

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package hardcaml_xilinx_reports
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val fold : init:'acc__0 -> latch:('acc__0 -> t Variantslib.Variant.t -> 'acc__1) -> carry:('acc__1 -> t Variantslib.Variant.t -> 'acc__2) -> lut:('acc__2 -> t Variantslib.Variant.t -> 'acc__3) -> muxf:('acc__3 -> t Variantslib.Variant.t -> 'acc__4) -> lutram:('acc__4 -> t Variantslib.Variant.t -> 'acc__5) -> srl:('acc__5 -> t Variantslib.Variant.t -> 'acc__6) -> 'acc__6
val map : t -> latch:(t Variantslib.Variant.t -> 'result__) -> carry:(t Variantslib.Variant.t -> 'result__) -> lut:(t Variantslib.Variant.t -> 'result__) -> muxf:(t Variantslib.Variant.t -> 'result__) -> lutram:(t Variantslib.Variant.t -> 'result__) -> srl:(t Variantslib.Variant.t -> 'result__) -> 'result__
val make_matcher : latch: (t Variantslib.Variant.t -> 'acc__0 -> (Base.Unit.t -> 'result__) * 'acc__1) -> carry: (t Variantslib.Variant.t -> 'acc__1 -> (Base.Unit.t -> 'result__) * 'acc__2) -> lut: (t Variantslib.Variant.t -> 'acc__2 -> (Base.Unit.t -> 'result__) * 'acc__3) -> muxf: (t Variantslib.Variant.t -> 'acc__3 -> (Base.Unit.t -> 'result__) * 'acc__4) -> lutram: (t Variantslib.Variant.t -> 'acc__4 -> (Base.Unit.t -> 'result__) * 'acc__5) -> srl: (t Variantslib.Variant.t -> 'acc__5 -> (Base.Unit.t -> 'result__) * 'acc__6) -> 'acc__0 -> (t -> 'result__) * 'acc__6
val to_rank : t -> Base.Int.t
val to_name : t -> Base.String.t
val descriptions : (Base.String.t * Base.Int.t) Base.List.t
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